(1) Field of the Invention
The present invention relates to a dynamic random access memory cell and a formation process thereof, and more particularly to a dynamic random access memory cell and a formation process thereof, in which a mixed stacked trench (MIST) type capacitor is provided.
(2) Description of the Prior Art
In the technical field of semiconductor memories, efforts have been focused on increasing the number of memory cells. For this purpose, it is important to minimize the area of each cell of the memory cell array formed on a chip which has a limited area.
It is therefore well known that providing one transistor and one capacitor in a memory cell in the smallest possible area is desirable. However, in a 1-transistor/1-capacitor cell, the capacitor occupies the most part of the area. Therefore, it is important that the area occupied by the capacitor is minimized, and at the same time, the capacitance of the capacitor is maximized, thereby making it possible to detect the stored data with a great reliability, so as to reduce the soft errors due to alpha particles.
In minimizing the occupation area of the capacitor and in maximizing the capacitance, a trench type capacitor is proposed. This trench type capacitor is constituted such that a cylindrical well is formed on the surface of the chip, and the capacitor electrode consists of the wall of the cylindrical well. Such a conventional trench type capacitor is disclosed in IEDM85 (pp 710-713, 1985) (International Electron Devices Meeting).
The trench type capacitor is formed in the following manner: a wafer in which an epitaxial layer is grown on a high concentration P.sup.+ substrate is used, and a cylindrical well is formed into the high concentration P.sup.+ layer. Then an insulating layer is formed on the wall of the well, and n.sup.+ polysilicon is filled into it, and a connection is formed to the source region of the transistor thereafter.
However, in forming the above described trench type capacitor, the thickness of the epitaxial layer is several micrometers and, therefore, the depth of the trench has to be deep enough to obtain a proper value of the capacitance, i.e., a value of capacitance suitable for the operation of the DRAM cell. Further, a thin oxide layer is formed on the wall of the trench, but, due to the sharpness of the corners of the bottom of the trench, the insulating layer can be damaged by the voltage supplied to the polysilicon which is filled into the trench for serving as the electrode of the capacitor. In addition, when the voltage on the polysilicon layer is varied, a strong inversion layer is formed between the above mentioned low concentration layer and the surface of the wall, thereby causing a punch-through phenomenon on the adjacent capacitors.
Another technique for maximizing the capacitance with
the limited memory cell has been proposed which is disclosed in pages 31 through 34 of IEDM (International Electron Devices Meeting) (S. Inoue et. al.) of 1989. This is a DRAM cell using a stacked capacitor (STC), and the description also includes a spread stacked capacitor (SSC) which is an improvement over the stacked capacitor.
The conventional techniques mentioned previously are described in FIGS. 3 and 4. FIG. 3 is a sectional view of a DRAM cell having a stacked capacitor, and in this DRAM cell, SiO.sub.2 is eliminated in order to simplify the structure of the memory cell. Here, reference numeral 21 indicates a storage electrode, 22 is a word line, and 23 is a field oxide layer.
As shown in the drawing, the storage electrode 21 of this DRAM cell uses only its own one memory cell region, and therefore, it cannot provide a sufficient storage capacitance within its limited own cell region for a memory device having a large capacity of over 16M bits.
FIG. 4 illustrates a structure in which each of storage electrodes 31, 32, 33 occupies two memory cell regions, thereby doubling the storage capacitance of the STC type memory cell of FIG. 3. In FIG. 4, reference numeral 31 indicates a storage electrode of a first memory cell; 32 is a storage electrode of a second memory cell; 33 is a storage electrode of a third memory cell; 34 is a bit line; 35 is a common drain region; 36 and 37 are word lines to serve as the gate electrodes; 38 and 39 are source electrodes, and 40 is a field oxide layer.
As shown in FIG. 4, the two memory cells, i.e., the first and second memory cells are formed between the field oxide layers 40. The spread stacked storage electrode 31 of the first memory cell is formed in such a manner that, in the vertical direction, it is extended between the bit line 34 and the storage electrode 32 of the second memory cell, and in the lengthwise direction, it is extended over a length equivalent to the two memory cell regions formed between the second storage electrode 32 and the third storage electrode 33.
In this arrangement, the storage capacitance Cs is greatly increased because it is proportionate to the area, but the distance between the first storage electrode 31 and the second storage electrode 32 and the third storage electrode 33 becomes too short, thereby causing the coupling of the electrodes to become too close, and consequently, causing disturbances in the stack structure.